Method for producing VLSI complementary MOS field effect transis

Details Method for producing VLSI complementary MOS field effect transis Method for producing VLSI complementary MOS field effect transis

1982-08-17

1984-07-17

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29577C, 148 15, 148187, 357 42, 357 91, H07L 2122, H07L 2978, H07L 21265

Patent

active

044597410

ABSTRACT:
Analog or digital MOS circuits in VLSI technology are produced by a method in which the manufacture of two troughs (5, 8) occurs with only one mask (3) used in production of the p-trough (5). The n-trough (8) is formed by a surface-wide implantation (7) of an ion selected from a group consisting of P, As and Sb. The channel implantation of the p-transistors occurs simultaneously. The field (11) and channel (12) implantation of the n-channel transistors is carried out with a silicon nitride mask (9), i.e., a LOCOS mask, and a double boron implantation (10a, 10b). The field implantation (16) of the p-channel transistors is carried out with arsenic (15). Advantages of this process sequence include reduction of parasistic edge capacitances at the source/drain edges with fewer masking steps.

REFERENCES:
patent: 4084311 (1978-04-01), Yasuoka et al.
patent: 4277291 (1981-07-01), Cerofolino et al.
patent: 4282648 (1981-08-01), Yu et al.
patent: 4314857 (1982-02-01), Aitken
patent: 4315781 (1982-02-01), Henderson
patent: 4369072 (1983-01-01), Bakeman et al.
L. C. Parrillo et al., "Twin-Tub CMOS--A Technology for VLSI Circuits", IEDM Technical Digest, (1980), Paper 29.1, pp. 752-755.
Y. Sakai et al., "High Packing Density, High Speed CMOS (Hi-CMOS) Device Technology", Japanese Journal of Applied Physics, vol. 18, Suppl. 18-1, (1978) pp. 73-78.
DeWitt Ong, "An All-Implanted CCD/CMOS Process", IEEE Transactions On Electron Devices, vol. ED-28 (1981), pp. 6-12.

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