Method for providing electrical isolating material in selected r

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29578, H01L 2712

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active

040054527

ABSTRACT:
An integrated circuit having dielectric isolation is fabricated by growing a double epitaxial layer of N-type semiconductive material onto a P-type substrate. A dielectric layer is formed over the epitaxial layer and thereafter the dielectric and the epitaxial growth are removed in selected isolation regions to expose the substrate. A metal layer is evaporated onto the device so that metal is deposited both on the exposed substrate material and on the dielectric layer. A dielectric is formed by selectively anodizing the metal deposited on the exposed substrate to provide electrical isolation between the remaining portions of the epitaxial growth. Because of the electrical insulating characteristics of the dielectric layer, the metal deposited on the dielectric layer is not anodized and may be removed using a compound that attacks the unanodized metal and has little effect on the anodized metal. Base and emitter elements are formed in the conventional manner to complete the integrated circuit.

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patent: 3737701 (1973-06-01), Hoeberechts
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Isolation Techniques for Ge Integrated Circuits by Light et al., IBM Tech. Discl. Bulletin vol. 9, No. 10 3/67 p. 1448.
"An Integration Approach for GE" by Light et al., IBM Tech Discl Bulletin vol. 9, No. 10 Mar. 67, pp. 1446-1447.

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