Sample and hold circuit

Details Sample and hold circuit Sample and hold circuit

1977-11-07

1980-06-24

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

328151, 328162, G11C 2702

Patent

active

042097177

ABSTRACT:
A low drift sample and hold circuit is disclosed comprising a transconductance input buffer coupled at its output to a plurality of CMOS inverters through a respective plurality of CMOS switches. The appropriate switches are momentarily addressed by a micro-processor while applying a respective input value to the buffer. The buffer is de-activated prior to the opening of the switch to prevent errors between the sampled and held values.

REFERENCES:
A C. Hansen, "Burst Mode Sampling Amplifier" IBM Technical Disclosure Bulletin vol. 14, No. 7 Dec. 1971 pp. 2196-2197.
J. Delarve et al., "Control Circuit For Sample-And-Hold Devices" IBM Technical Disclosure Bulletin vol. 19 No. 11 Apr. 1977 pp. 4211-4212.

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