1988-07-13
1990-01-09
Larkins, William D.
357 20, 357 238, 357 41, 357 51, 357 52, 357 56, 357 59, H01L 2978, H01L 2702, H01L 2904
Patent
active
048931594
ABSTRACT:
This protected MOS transistor circuit has a p-type semiconductor substrate, VSS terminal, input MOS transistor, first resistor connected to the gate electrode of transistor, and MOS transistor which has a gate electrode connected to the VSS terminal and a current path connected between the VSS terminal and a junction of the first resistor and the gate electrode of the input MOS transistor. This protected MOS transistor circuit further has a second resistor connected in series with the first resistor, and pn-junction diode connected reversely between the VSS terminal and the junction of the first and second resistors.
REFERENCES:
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patent: 4763184 (1988-08-01), Krieger et al.
Keller, "Protection of MOS Integrated Circuit from Destruction by Electrostatic Discharge", pp. 73-80, Proceedings of the 1980 Electrical Overstress/Electrostatic Discharge Symposium.
Fujishin et al., "Optimized ESD Protection Circuits for High-Speed MOS/VLSI," IEEE Journal of Solid-State Circuits, vol. SC-20, No. 2, pp. 594-596, Apr. 1985.
Ariizumi Shoji
Kondo Takeo
Masuoka Fujio
Segawa Makoto
Suzuki Youichi
Kabushiki Kaisha Toshiba
Larkins William D.
Ngo Ngan Van
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