Peripheral interrupt priority resolution in a micro program data

Details Peripheral interrupt priority resolution in a micro program data Peripheral interrupt priority resolution in a micro program data

1975-06-06

1977-01-25

Malzahn, David H.

Communications: electrical

Digital comparator systems

G06F 918

Patent

active

040053911

ABSTRACT:
A peripheral interrupt priority technique in a micro program system is disclosed which system employs two levels of subinstruction sets. The first level of subinstructions, or micro instructions, is implemented by a second level of control instructions that can be stored in a processor read-only memory. The respective micro instructions are made up of varying numbers of syllables according to the function of the particular micro instructions. The various types of micro instruction syllables are stored in a micro instruction memory to be fetched therefrom in sequence in accordance with the requirements of a particular macro instruction or subject instruction. In this manner, a variety of micro instructions can be created by selecting a plurality of different syllables from the micro instruction memory. A different control instruction syllable is provided to specify each combination of the function to be performed and the source and destination registers to be used with the particular buses in the processor.
A particular type of micro instruction is provided to control a number of data transfers within the processor and to or from memory and the input/output periphery and also to halt such data transfer upon fulfillment of a given condition. This type of micro instruction can also be employed to resolve priority of requests for service by different peripheral units, the action ending when the request having the highest priority is found.

REFERENCES:
patent: 3434111 (1969-03-01), Schmidt et al.
patent: 3599162 (1971-08-01), Byrns et al.
patent: 3836889 (1974-09-01), Kotok et al.

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