1978-04-04
1980-04-22
Edlow, Martin H.
357 55, 357 90, H01L 2974
Patent
active
041997719
ABSTRACT:
In a static induction transistor of the type wherein carriers are injected from a source region to a drain region across a potential barrier induced in a current channel, and wherein the height of the potential barrier can be varied in response to a gate bias voltage applied to a gate to thereby control the magnitude of a drain current of the transistor. The product of the channel resistance R.sub.c and the true transconductance (G.sub.m) of the transistor is maintained less than one and the product of the true transconductance and the series resistance R.sub.s of the transistor is maintained greater than or equal to one in the main operative state of the transistor. The series resistance R.sub.s is the sum of a resistance of the source, a resistance from the source to the current channel, and the channel resistance from the entrance of the current channel to the position of maximum value (extrema point) of the potential barrier in the current channel. This static induction transistor has the advantage that the current-voltage characteristic curve is nearly linear over a very wide range of drain current including the low drain current region.
REFERENCES:
patent: Re28500 (1975-07-01), Bresee
patent: 2778956 (1957-01-01), Dacey
patent: 3657573 (1972-04-01), Maute
patent: 3938241 (1976-02-01), George
patent: 3968450 (1976-07-01), Suzuki
patent: 3977017 (1975-01-01), Ishitani
patent: 4106044 (1978-08-01), Yoshida
patent: 4115793 (1978-09-01), Nishizawa
Nishizawa Jun-ichi
Yoshida Takashi
Edlow Martin H.
Nippon Gakki Seizo Kabushiki Kaisha
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