System and method for reducing power consumption in high frequen

Details System and method for reducing power consumption in high frequen System and method for reducing power consumption in high frequen

1996-08-14

1998-06-02

Auve, Glenn A.

395556, G06F 132

Patent

active

057615179

ABSTRACT:
A system and method are provided which automatically change the output of an oscillator clock prior to its input to dynamic logic circuit elements as a system clock signal. The oscillator clock signal is controlled based upon a signal generated by a sensor which determines the power consumption of the integrated circuit. The frequency of the clocked signal is reduced (or increased) incrementally based upon the output of the sensor which detects the level of a specific circuit characteristic, relating to electrical power consumption. A pattern generator is used to input a digital signal to a series of interconnected registers which make up a loadable shift register. The output of the pattern generator is based upon the input from the sensor. The bits shifted through the shift register are ANDed with the oscillator clock signal to control the frequency of the system clock.

REFERENCES:
patent: 4093871 (1978-06-01), Plumb et al.
patent: 4716551 (1987-12-01), Inagaki
patent: 5073838 (1991-12-01), Ames
patent: 5086387 (1992-02-01), Arroyo et al.
patent: 5222239 (1993-06-01), Rosch
patent: 5465367 (1995-11-01), Reddy et al.
patent: 5511203 (1996-04-01), Wisor et al.
patent: 5628001 (1997-05-01), Cepuran
patent: 5630148 (1997-05-01), Norris
patent: 5664201 (1997-09-01), Ikedea
IBM Technical Disclosure Bulletin, vol. 38, No. 5, May, 1995, pp. 465-468, "Differential Current Switch Data Interface to an EDA Drive Bipolar Embedded Array".
IBM Technical Disclosure Bulletin, vol. 38, No. 1, Jan., 1995, pp. 27-34, "Algorithm for Incremental Timing Analysis".
IBM Technical Disclosure Bulletin, vol. 33, No. 12, May, 1991, pp. 439-441, "Efficient Power-Supply Decoupling Scheme for Dynamic Rams".
IBM Technical Disclosure Bulletin, vol. 29, No. 10, Mar., 1987, pp. 4527-4528, "Infrared Transmitter with Dual Power Levels".
IBM Technical Disclosure Bulletin, vol. 22, No. 1, Jun., 1979, pp. 140-141, 142-143, "Cache Bit Selection Circuit".

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