Inter-chip bus with fair access for multiple data pipes

Details Inter-chip bus with fair access for multiple data pipes Inter-chip bus with fair access for multiple data pipes

1996-10-21

1998-06-02

Harvey, Jack B.

395309, 395285, 395824, 395850, G06F 1337, G06F 1342

Patent

active

057614571

ABSTRACT:
A computer system is provided comprising a first expansion bus which operates according to a first transfer protocol and adapted to couple to one or more peripheral devices. A central processing unit and a bus bridge are operatively coupled to the first expansion bus. A second bus including a second transfer protocol is coupled to the bus bridge. A plurality of peripheral devices compatible with the second transfer protocol are coupled to the second bus. The bus bridge is configured to communicate with the plurality of peripheral devices in a round-robin ping-pong fashion, wherein the bus bridge is configured to generate address/data pairs to at least one port of one of the plurality of peripheral devices, and thereafter receive address/data pairs from the at least one port of the one of the plurality of peripheral devices. The bus bridge is further configured to generate and receive address/data pairs sequentially to ports in at least a subset of the plurality of peripheral devices in a round robin fashion. The address/data pairs comprise an address which includes command/data information, data position information, and port address information. The data position information identifies a position of the corresponding data in the address/data pair.

REFERENCES:
patent: 5444847 (1995-08-01), Iitsuka
PCI Local Bus Multimedia Design Guide, Revision 1.0, Mar. 29, 1994, pp. 1-40.
Peripheral Components, Intel, Dec. 1994 pp. ix, 1-1 through 1-72.
Peripheral Components, Intel, 1995, pp. ix, 1-1 through 1-72.

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