Flip-flop circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307279, 307291, 307289, H03K 3289, H03K 326, H03K 329

Patent

active

050251740

ABSTRACT:
A flip-flop circuit comprises a first transfer gate receiving input data and being conductive responsive to a clock signal, a second transfer gate receiving an inverted input data and being conductive responsive to said clock signal, a third transfer gate receiving said input data and being conductive responsive to an inverted clock signal, and a fourth transfer gate receiving said inverted input data and being conductive responsive to said inverted clock signal. First and second inverters are cross-coupled across output nodes of said first and second transfer gates to serve as a latch circuit. Third and fourth inverters are cross-coupled across output nodes of said third and fourth transfer gates to serve as a latch circuit. A selector selects either the outputs of the first and second transfer gates, or the outputs of the third and fourth transfer gates, as output data and inverted output data of the flip-flop circuit, in accordance with said clock and inverted clock signals.

REFERENCES:
patent: 4777623 (1988-10-01), Shimazu et al.
IEEE Journal of Solid-State Circuits, vol. SC-22; No. 3; Jun. 1987; pp. 385-389 "5-Gbit/s Si Integrated Regenerative Demultiplexer and Decisions Circuit;" Clawin et al.

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