Method and apparatus for facilitating instruction processing of

Details Method and apparatus for facilitating instruction processing of Method and apparatus for facilitating instruction processing of

1986-03-27

1988-01-26

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 1300, G06F 930

Patent

active

047220503

ABSTRACT:
A computer having a cache memory and a main memory is provided with a transformation unit between the main memory and the cache memory so that at least a portion of an information unit retrieved from the main memory may be transformed during retrieval of the information (fetch) from a main memory and prior to storage in the cache memory (cache). In a specific embodiment, an instruction may be predecoded prior to storage in the cache memory. In another embodiment involving a branch instruction, the address of the target of the branch is calculated prior to storing in the instruction cache. The invention has advantages where a particular instruction is repetitively executed since a needed decode operation which has been partially performed previously need not be repeated with each execution of an instruction. Consequently, the latency time of each machine cycle may be reduced, and the overall efficiency of the computing system can be improved. If the architecture defines delayed branch instructions, such branch instructions may be executed in effectively zero machine cycles. This requires a wider bus and an additional register in the processor to allow the fetching of two instructions from the cache memory in the same cycle.

REFERENCES:
patent: 4437149 (1984-03-01), Pomerene et al.
patent: 4521850 (1985-06-01), Wilhite et al.

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