Minimum latency asynchronous data path controller in a digital r

Details Minimum latency asynchronous data path controller in a digital r Minimum latency asynchronous data path controller in a digital r

1997-05-09

1998-06-02

Elmore, Reba I.

Excavating

371 377, 371 4012, G11C 2900

Patent

active

057612200

ABSTRACT:
An asynchronous data path controller for reading, correcting, and transferring data on-the-fly from a digital recording device to a host system. Central to the data path controller is a RAM for storing the data as it is read from the recording device and a RAM controller for arbitrating access to the RAM. An error correcting system reads the data from the RAM, corrects the data, and then restores the corrected data back to the RAM before it is transferred to the host system. The error correcting system includes an error syndrome generator and a error location and error value generator. In a first embodiment, the data codewords, comprised of user data and redundancy symbols, are stored from the recording device into the RAM. The error syndrome generator reads the codewords from the RAM, generates error syndromes, and transfers the error syndromes to the error location and error value generator. In an alternative embodiment, the error syndrome generator receives the codewords directly from the recording device. Only the user data and the error syndromes are stored into the RAM. In both embodiments, uncorrected data is read from the RAM, corrected in response to the error syndromes, and the corrected data stored into the RAM for subsequent transfer to the host system. The steps of reading data from the recording device, correcting it, and transferring it to the host occurs concurrently and asynchronously.

REFERENCES:
patent: 4494234 (1985-01-01), Patel
patent: 4730321 (1988-03-01), Machado
patent: 4733396 (1988-03-01), Baldwin et al.
patent: 4833679 (1989-05-01), Anderson et al.
patent: 4835775 (1989-05-01), Seroussi
patent: 4849975 (1989-07-01), Patel
patent: 4866716 (1989-09-01), Weng
patent: 4890287 (1989-12-01), Johnson et al.
patent: 4920539 (1990-04-01), Albonesi
patent: 5241546 (1993-08-01), Peterson et al.
patent: 5243604 (1993-09-01), Tsang et al.
patent: 5267241 (1993-11-01), Kowal
patent: 5280488 (1994-01-01), Glover et al.
patent: 5384786 (1995-01-01), Dudley et al.
patent: 5537421 (1996-07-01), Dujari et al.

Affiliated with

Also associated with

Rating

Minimum latency asynchronous data path controller in a digital r does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Minimum latency asynchronous data path controller in a digital r, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Minimum latency asynchronous data path controller in a digital r will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1469583