Parallel data processing system using a plurality of processing

Details Parallel data processing system using a plurality of processing Parallel data processing system using a plurality of processing

1994-06-17

1996-04-09

An, Meng-Ai

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395250, 395840, 36493141, 36493148, 36493151, 3649405, 3642386, 3642387, 3642389, 364239, 364271, 3642712, 364DIG1, G06F 1300, G06F 1516, G06F 1531

Patent

active

055069983

ABSTRACT:
A parallel data processing system performs a data processing by using a plurality of data processing units, namely, processor elements, synchronously. The parallel data processing system comprises a plurality of data processing units, a plurality of trays, and a clock generator. The plurality of trays are connected to respective data processing units and have a function of storing a plurality of data and a function of transmitting the data. The clock generator is producing a clock so that the data transfer between the trays and between the trays and the data processing units, and the data processing in the data processing unit is executed synchronously. Data are transferred between trays during the period in which they are processed, thus substantially eliminating the data transmission time. Furthermore, the interim result of the operation is stored in the tray and thus when the later operation needs the interim result, the interim result stored in the tray is efficiently used without the need to access the memory provided in the data processing apparatus.

REFERENCES:
patent: 4195351 (1980-03-01), Barnes et al.
patent: 4434463 (1984-02-01), Quinquis et al.
patent: 4467422 (1984-08-01), Hunt
patent: 4468733 (1984-08-01), Oka et al.
patent: 4663706 (1987-05-01), Allen et al.
patent: 4683563 (1987-07-01), Rouse et al.
patent: 4763254 (1988-08-01), Mori et al.
patent: 4816993 (1989-03-01), Takahashi et al.
patent: 4821174 (1989-04-01), Webb et al.
patent: 4922418 (1990-05-01), Dolecek
patent: 4979096 (1990-12-01), Ueda et al.
patent: 5168572 (1992-12-01), Perkins
patent: 5367642 (1994-11-01), Dally
patent: 5388220 (1995-02-01), Okabayashi
Proc. Int. Conf. on Wafer Scale Integration, 23 Jan. 1990, San Francisco, USA, pp. 220-228, Ramaswamy R. et al.
IEEE Transactions on Acoustics, Speech and Signal Processing, vol. 37, No. 12, Dec., 1989, New York US, pp. 1967-1979, J.-N. Hwang et al., `A Systolic Neural Network Architecture for Hidden Markov Models`.
Journal of VLSI Signal Processing, vol. 1, No. 3, Nov. 1989, Dordrecht NL, pp. 221-251, Hwang J. N. et al., `Parallel Algorithms/Architectures for Neural Networks`.

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