Semiconductor nonvolatile memory device in which high capacitanc

Details Semiconductor nonvolatile memory device in which high capacitanc Semiconductor nonvolatile memory device in which high capacitanc

1996-05-20

1998-06-02

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 3651852, 36518521, 36518525, G11C 1606

Patent

active

057611246

ABSTRACT:
A CMOS latch circuit is used as a sense amplifier, and a switch circuit is connected between the input/output of the sense amplifier and a data line or bit line and is turned OFF immediately before or after the amplifying operation of the sense amplifier. During the amplifying operation of the sense amplifier, the data line or bit line having a large parasitic capacitance, as a result of being connected, typically, to a large number of memory transistors, is electrically disconnected or electrically isolated from the sense amplifier. As a result, the sense amplifier may have its input/output parasitic capacitor driven so that its operation speed can be increased while reducing its power consumption.

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IEEE 1992 Symposium on VLSI Circuits Digest of Technical Papers, "A Quick Intelligent Program Architecture for 3V-Only NAND-EEPROMs", T. Tanaka, et al., pp. 20-21.
"Fundamentals of MOS Digital Integrated Circuits", John P. Uyemura, pp. 414 and 547.

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