Method for analyzing and efficiently eliminating timing problems

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39550007, G06F 1124

Patent

active

059830069

ABSTRACT:
This invention illustrates a method is provided for analyzing cross-coupling between an attacker signal line, upon which an attacker signal resides, and a victim signal line, upon which a victim signal resides. The method in this invention comprises the acts of selecting the victim signal, selecting the attacker signal, performing timing filtering upon a number of signal lines in order to identify a set of potential attacker signals, performing logic filtering upon a number of signal lines to identify a second set of potential attacker signals, and reducing the effects of the cross-coupling between the attacker signal line and the victim signal line.

REFERENCES:
patent: 5535133 (1996-07-01), Petschauer et al.
`Analysis, reduction and Avoidance of Crosstalk on VLSI Chips`, Tilmann Stohr et al., ACM Journal I-58113-021-x/98/4, pp. 211-218, 1998.
`Results of Analyzing VLSI Interconnect Structures by a methodology Based on Mixed Frequency-Time Domain`, Salvador Perdomo and antonio Nunez, IEEE 1993, 1066-1409-93, pp. 409-413, 1993.
Lassszlo Gal, `On-Chip Cross Talk--the New Signal Integrity Challenge`, IEEE 1995 Custon Integrated Circuits Conference, pp. 251-254, 1995.
Selected pp. (143, 330 and 334) from the Hewlett Packard 1994 Test & Measurements Catalog, 1994.

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