Integrated logic network with simplified programming

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364900, 34082583, G06F 738

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active

044882467

ABSTRACT:
An electrically programmable logic network having an AND matrix, and OR matrix, and interfact circuits for inputting, outputting, and making connections between the matrices. To simplify programming of the matrices and to effect programming simultaneously for both matrices, there is provided a decoder designating an output column of the AND matrix and a corresponding input line of the OR matrix. The programming of the input lines of the AND matrix and of the output columns of the OR matrix is carried out by using the Ai variable inputs to the AND matrix and the Si outputs from the OR matrix as inputs, to the programming and with the same meaning as these Ai inputs and Si outputs have during the normal utilization of the network.

REFERENCES:
patent: 3987286 (1976-10-01), Muehldorf
patent: 4034356 (1977-07-01), Howley et al.
patent: 4041459 (1977-08-01), Horninger
patent: 4094012 (1978-06-01), Perlegos et al.
patent: 4130900 (1978-12-01), Watanabe
patent: 4313106 (1982-01-01), Hsu
IEEE Journal of Solid-State Electronics, vol. SC-10, No. 5, Oct. 1975; Honger: "A High-Speed ESFI SOS Programmable Logic Array with an MNOS Version", pp. 331-336.
Electronic Design, vol. 18, Sep. 1975; (Rochelle Park), Cavlan et Cline: "Field-PLAs Simplify Logic Designs", pp. 84-90.

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