Amplifier MOS biasing circuit for a avoiding latch-up

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

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327543, H03K 17687

Patent

active

060140534

ABSTRACT:
An amplified MOS biasing apparatus and method for avoiding latch-up within an integrated circuit. An amplifier receives a plurality of voltages and multiplies the voltages by a gain so as to generate a plurality of amplified voltages. A comparator compares the plurality of voltages and generates signals indicating which is greatest and which is smallest. A switch connects the greatest of the voltages to N-wells in PMOS transistors and connects the smallest of the voltages to P-wells in NMOS transistors to discourage parasitic diodes, within the PMOS and NMOS transistors, from conducting excessive amounts of current.

REFERENCES:
patent: 5371419 (1994-12-01), Sundby
patent: 5402375 (1995-03-01), Horiguchi et al.
patent: 5608344 (1997-03-01), Marlow

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