Pipe lined static router and scheduler for configurable logic sy

Details Pipe lined static router and scheduler for configurable logic sy Pipe lined static router and scheduler for configurable logic sy

1997-02-24

1998-12-15

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364489, G06F 9455

Patent

active

058505377

ABSTRACT:
A configurable logic system programmed to model a logic design comprises an array of programmable logic modules each configured to perform a partition block of the logic design and a module interconnect providing connections between the modules. The interconnect enables transmission of global links between the partition blocks of the modules. The modules time division multiplex the global links, with a destination module then demultiplexing the global links allowing the links to pass through to another FPGA. The modules are configured to transmit individual ones of the global links at time intervals determined in response to a ready time of the individual links. The ready times of individual global links are determined in response to receipt of parent global links and signal propagation delays across the modules. A parent of a particular global link is a link that affects a logic value of the global link. The present invention allows computation and communication simultaneously. Previously, the calculations and communications were divided into discrete phases within each emulation clock period.

REFERENCES:
patent: 4495590 (1985-01-01), Mitchell, Jr.
patent: 4506341 (1985-03-01), Kalter et al.
patent: 4697241 (1987-09-01), Lavi
patent: 5109353 (1992-04-01), Sample et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5268598 (1993-12-01), Pedersen et al.
patent: 5442306 (1995-08-01), Woo
patent: 5444394 (1995-08-01), Watson et al.
patent: 5473266 (1995-12-01), Ahanin et al.
patent: 5483178 (1996-01-01), Costello et al.
patent: 5485103 (1996-01-01), Pedersen et al.
patent: 5513338 (1996-04-01), Alexander et al.
patent: 5572710 (1996-11-01), Asano et al.
Deiss, Connectionism without the Connections, IEEE, pp. 1217-1221, Jun. 27, 1994
Dominques-Castro et al., Architectures and Building Blocks for CMOS VLSI Analog "Neural" Programmable Optimizers, IEEE, pp. 1525-1528, May 1992.
Fornaciari, An Automatic VLSI Implementation of Hopfield ANNs, IEEE, pp. 499-502, Aug. 1994.
Bailey et al., Why VLSI Implementations of Associative VLCNs Require Connection Multiplexing, IEEEpp. 173-180, Jul. 1988.
D. Bursky, "Fast Simulator Expands to Mimic 4 Million Gates," Electronic Design, p. 23 (Dec. 29, 1986).
D. Bertsekas, et al., "Messages and Switching," Routing in the Codex Network, and Using Antifuse Programming for Gate-Array Density and Flexibility, Data Networks, (Englewood Cliffs, NJ: Prentice-Hall), pp. 8-14, 91-95, and 403-405 (1987).
D. Bursky, "Using Antifuse Programming for Gate-Array Density and Flexibility, an FPGA Family Also Delivers Masked-Array Performance. FPGAs Mirror Masked Gay-Array Architecture," Electronic Design, pp. 63-67, (Nov. 21, 1991).
P. Kermani, et al., "Virtual Cut-Through: A New Computer Communication Switching Technique," Computer Networks, 3:267-286, (1979, Oct.).
R. Murgai, et al., " Logic Synthesis for Programmable Gate Arrays," 27th ACM/IEEE Design Automation Conference, pp. 620-625 (1990).
S. Singh, et al., "Optimization of Field-Programmable Gate Array Logic Block Architecture for Speed," IEEE Custom Integrated Circuits Conference, pp. 611-616 (1991).
W.J. Dally, "Virtual-Channel Flow Control," IEEE Transactions on Parallel and Distributed Systems, 3(2):194-205 (1992).
J. Rose, et al., "Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency," IEEE Journal of Solid-State Circuits, 25(5):1217-1225 (1990).
Y.C. Wei, et al., "Multiple-Level Partitioning: An Application to the Very Large -Scale Hardware Simulator," IEEE Journal of Solid-State Circuits, 26(5):706-716 (1991).
Z. Lavi, "The SuperSim -An Ultrafast Hardware Logic Simulator,", IFIP Workshop on CAD Engines, Tokyo (Jun. 6-9, 1987).
R. Wittenberg, "Three Newcomers Stir Up Hardware Accelerator Market," Circle Reader Service.
A.J.G. Hey, "Supercomputing with Transputers -Past, Present and Future," Computer and Architecture News Int. Conf. Supercomputing, 18(3):479-489 (1990).
O.P. Agrawal, "Field Programmable Gate Arrays (FPGAs) Provide Asic System Designers Control of Their Design Destiny," ElectroConference Record, 15:353-361 (1990).
J. Babb, et al. "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators," IEEE Workshop on FPGAs for Custom Computing Machines, 5(4):142-151 (1993).
C. Erickson, et al., "Logic Cell Array", The Programmable Gate Array Design Handbook, (XILINX, First Edition), pp. 1.9-1.14 (1986).
D.E. Van Den Bout, et al., "AnyBoard: An FPGA-Based, Reconfigurable System," IEEE Design & Test of Computers, pp. 21-30 (1992).

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