Method and apparatus for reducing cache snooping overhead in a m

Details Method and apparatus for reducing cache snooping overhead in a m Method and apparatus for reducing cache snooping overhead in a m

1995-06-05

1998-12-15

Chan, Eddie P.

395449, 395461, G06F 1212

Patent

active

058505342

ABSTRACT:
A memory system for reducing cache snooping overhead for a multilevel cache system has a highest cache level connected to a main memory and a lowest cache level connected to a processor or other memory accessing device. Each intermediate level cache is connected to a cache level one level above and below that cache. The highest cache level detects a memory access on a shared memory bus, and determines if that memory access resides in that cache. If there is a hit in that cache, the highest cache level checks a hit flag for every storage location within that highest level cache to determine if the memory access also hits a storage location within the next lower cache level. If there is a hit in the next lower cache level, that cache also checks a hit flag for every storage location within that cache to determine if the memory access also hits a storage location within the next lower cache level. This process continues until the memory access does not hit a particular cache level or until the lowest cache level is reached.

REFERENCES:
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patent: 5369753 (1994-11-01), Tipley
patent: 5530832 (1996-06-01), So et al.
IBM Technical Disclosure Bulletin, "Extended L2 Directory For L1 Residence Recording", vol. 34 No. 8, Jan. 92.
IBM Technical Disclosure Bulletin, vol. 36, No. 12, Dec. 1, 1993, pp. 441-445, XP000419025 "Handling Reservations in Multiple-Level Cache".

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