Method and apparatus for improving bus efficiency by enabling ar

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395280, 395287, 364240, 320 44, G06F 1300

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058505300

ABSTRACT:
The present invention provides a system that selectively allows an arbitration cycle to occur only when specific data is ready for transfer. That is, a flag register is provided and its output is ANDed with a bus request signal from a bus device. An arbiter will accept a bus request and initiate an arbitration cycle only when the state of a bit in the flag register indicates that actual completion data exists for the requesting device.

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