Semiconductor switch array with electrostatic discharge protecti

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material

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Details

257356, H01L 2362

Patent

active

060139234

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a method of protecting a semiconductor switch array from electrostatic discharge damage and to a semiconductor switch array incorporating electrostatic discharge protection.


BACKGROUND ART

Electrostatic discharge (ESD) damage is a well known phenomenon and can occur during the fabrication of semiconductor devices such as metal-oxide semiconductor (MOS) structures. In structures of this nature, ESD damage can result in gate insulating layer breakdown, large shifts in threshold voltage and large leakage currents between the gate and source electrodes or gate and drain electrodes.
ESD damage is a more pronounced problem during the fabrication of thin film transistor (TFT) switch arrays for use in liquid crystal displays or in flat panel detectors for radiation imaging. This is due to the fact that the TFT switches are formed on an insulating substrate (typically glass) and thus, the source and drain electrodes may charge to a very high voltage. Also, because peripheral circuits to which the TFT switch array is to be connected are generally not formed on the same substrate as the TFT switch array, the gate and source lines must extend from the TFT switch array sufficiently to allow the peripheral circuits to be connected to the TFT switch array via wire bonding pads. Any static charge picked up by the gate and source lines is transferred to the gate and source electrodes of the TFT switches as well as to the intersecting nodes of the gate and source lines where the static charge is held. If the static charge reaches a high enough level, the dielectric gate insulating layer between the gate and source electrodes may breakdown. Even if this breakdown can be avoided, the voltage differential between the gate and source electrodes or gate and drain electrodes caused by this held static charge may cause the threshold voltage of the TFT switches to shift in either a positive or negative direction.
Recently, a large amount of attention has been given to the problems resulting from ESD damage especially in active matrix liquid crystal displays and flat panel detectors for radiation imaging. It is now believed that ESD damage is also caused by equipment related problems during the fabrication, handling and testing of these types of devices. The trends to use higher throughput equipment with higher speed substrate handling as well as to downscale during the fabrication process to reduce metal line width and reduce parasitic capacitance in the TFT switches decrease ESD immunity.
One common ESD damage protection circuit used with TFT switch arrays makes use of closed shorting bars surrounding the TFT switch array to link all of the source lines and the gate lines of the TFT switch array together. The shorting bar associated with the gate lines is formed at the time the gate lines are formed while the shorting bar associated with the source lines is formed at the time the source lines are formed. The two shorting bars are electrically connected through vias formed in the TFT switch array structure. Because the shorting bars connect the gate and source electrodes of all of the TFT switches in the array, the gate and source electrodes remain at the same potential throughout the fabrication process. This prevents any voltage differentials from occurring across the gate and source electrodes and therefore, inhibits ESD damage at these electrodes.
Once the TFT switch array has been completely fabricated, the shorting bars are removed by cutting off part of the glass substrate where the shorting bars located. This cutting process is done before the individual TFT switches are tested and before the gate and source lines are connected to peripheral circuits.
Although the above ESD damage protection circuit is widely used, once the shorting bars have been removed, to ESD damage protection remains. This poses problems since ESD damage often occurs during testing of the TFT switches and during bonding of the gate and source lines to peripheral equipment. This is in view of the fact

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Sang U. Kim, "ESD induced gate oxide damage during wafer fabrication process," Journal of Electrostatics, (Dec., 1993).

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