Clock skew minimization system and method for integrated circuit

Details Clock skew minimization system and method for integrated circuit Clock skew minimization system and method for integrated circuit

1996-08-20

1998-06-02

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

257778, 257685, 257686, 438108, H01L 2348, H01L 2352, H01L 2940, H01L 2302

Patent

active

057604789

ABSTRACT:
A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, "quiet busses" are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance.

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H.W. Gruber et al, "Compact Stacked Memory Package", 2/88, v. 30, pp. 428-429, IBM Technical Disclosure Bulletin.

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