Method for preventing poisoned vias and trenches

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

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438740, 438743, 438723, 216 18, 216 39, 216 67, 216 79, H01B 1300

Patent

active

060135816

ABSTRACT:
A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an plasma treatment, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.

REFERENCES:
patent: 5429710 (1995-07-01), Akiba et al.
patent: 5926732 (1999-07-01), Matsuura

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