Power failure early warning circuit for microprocessor with CMOS

Boots – shoes – and leggings

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365226, G06F 100, G11C 1300

Patent

active

043756638

ABSTRACT:
A circuit for preventing data transfers to a RAM by a microprocessor when primary ac power fails also puts the RAM in standby after a period adequate to complete any data transfer started. The sequence is provided by providing a first signal to the microprocessor transfer enable line upon loss of primary power. A second signal is provided for the enable line of the RAM after a predetermined delay but before decay of the dc power to the RAM.

REFERENCES:
patent: 4096560 (1978-06-01), Footh
patent: 4122359 (1978-10-01), Breikss

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