Variable delay circuit

Details Variable delay circuit Variable delay circuit

1997-08-04

1999-11-09

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327287, 327277, H03K 513

Patent

active

059822147

ABSTRACT:
A variable delay circuit for a semiconductor memory device includes an input buffer for converting a digital input signal to an analog signal and buffering the resultant analog signal, an analog delay unit for delaying the analog signal outputted from the input buffer unit for a certain time, and an output buffer unit for converting the delayed analog signal to a digital signal and buffering the resultant digital signal. The analog delay unit is composed of a CMOS inverter, a plurality of operational transconductance amplifier-capacitor delay elements, and an output inverter, to form a second-order Bessel filter. An O.T.A and an inverter may be additionally provided between the plurality of O.T.A.'s for thereby decreasing a parasitic effect of the capacitors connected to the outputs of each of the plurality of O.T.A.'s in the analog delay unit. The delay circuit serves to obtain a desired delay time by varying a control voltage irrespective of unstable time delay values of components caused by the fabrication process.

REFERENCES:
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patent: 4801827 (1989-01-01), Metz
patent: 4820943 (1989-04-01), Makino et al.
patent: 4821003 (1989-04-01), Kameya
patent: 4890022 (1989-12-01), Endo
patent: 5461335 (1995-10-01), Tsuchiya
patent: 5467041 (1995-11-01), Baba et al.
patent: 5495197 (1996-02-01), Hayashi et al.

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