Digital phase lock loop

Details Digital phase lock loop Digital phase lock loop

1997-11-14

1999-11-09

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327278, H03K 513

Patent

active

059822139

ABSTRACT:
A clock multiplier (40) comprises a digital phase lock loop circuit having a single variable delay stage (44) for generating high and low phases for the output clocks. The variable delay stage (44) includes a commutator 64 which chooses between the signal propagating on first and second delay paths (52 and 54). The delay on the delay paths can be incrementally adjusted using capacitors (58 and 61) selectively enabled between the path and ground. If the variable delay is insufficient to lock the output to the reference clock, a prescaler (72) automatically divides the output as needed. A stutter mode prevents short pulses, caused by a transition of the reference clock arriving shortly after the transition of the output clock to a low state, from being passed to the clock multiplying circuitry. The clock multiplier (40) may use a free running mode after lock is obtained, where adjustments are made relative to the degree of difference between the output clock and the reference clock.

REFERENCES:
patent: 5327031 (1994-07-01), Marbot et al.
patent: 5548235 (1996-08-01), Marbot
patent: 5764092 (1998-06-01), Wada et al.
patent: 5805003 (1998-09-01), Hsu
A Portable Clock Multiplier Generator Using Digital CMOS Standard Cells, by Michel Combes, Karim Dioury and Alain Greiner.
"These de Doctorat de l'Universite Pierre et Marie Curie (Paris 6)", Combes, M (Dec. 12, 1994).

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