Substantially planar semiconductor topography using dielectrics

Details Substantially planar semiconductor topography using dielectrics Substantially planar semiconductor topography using dielectrics

1997-03-21

1998-12-15

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257296, 257759, 257760, 438624, 438631, 438699, 438697, 438763, H01L 2358

Patent

active

058501053

ABSTRACT:
A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower regions. Subsequent chemical mechanical polishing produces a substantially planar surface.

REFERENCES:
patent: 5508233 (1996-04-01), Yost et al.
patent: 5523615 (1996-06-01), Cho et al.
patent: 5671175 (1997-09-01), Liu et al.

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