Method for constructing a planar equal path length clock tree

Details Method for constructing a planar equal path length clock tree Method for constructing a planar equal path length clock tree

1996-03-26

1998-12-15

Crane, Sara W.

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

With electrical circuit layout

257208, 327293, 364491, 395552, H01L 2710

Patent

active

058496106

ABSTRACT:
A method of constructing a planar equal path length clock tree. Prior computer-generated methods of creating low-skew clock trees required that clock sinks be uniformly distributed throughout the circuit. Moreover, the tree produced would often be non-planar, thus increasing layout design complexity and cost. The present invention provides for a method of automatically producing a planar clock tree with equal path lengths from each clock sink to the clock source. A first branch wire is formed between the clock source and the clock sink that is a farthest distance from the clock source. Thereafter, the remaining uncoupled clock sinks are coupled to the clock tree according to a maximum rule and a minimum rule. Thus a planar equal path length clock tree is formed. The planar equal path length clock tree is transformed in to a rectilinear clock tree, including horizontal and vertical wires, by using a line search algorithm. The rectilinear clock tree may then be optimized for tolerable clock skew by a cut-and-link method.

REFERENCES:
patent: 5519351 (1996-05-01), Matsumoto
patent: 5557779 (1996-09-01), Minami
patent: 5691662 (1997-11-01), Soboleski et al.
Qing Zhu; "Planar Clock Routing for Chip and Package Co-Design", IEEE Transactions on VLS1 Systems, Jun. 1996, pp. 0-33.

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