Manufacturing high speed low leakage radiation hardened CMOS/SOI

Details Manufacturing high speed low leakage radiation hardened CMOS/SOI Manufacturing high speed low leakage radiation hardened CMOS/SOI

1990-02-16

1991-06-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 26, 437 62, 437 67, 437 84, 437240, 437982, 148DIG150, 148DIG133, H01L 21336

Patent

active

050249657

ABSTRACT:
A method of fabricating high speed, low leakage, radiation hardened integrated circuit semiconductor devices. In accordance with the method a SIMOX (separation by ion implantation of oxygen) wafer is masked with a separation mask to form silicon islands. The separation mask forms groups of N-channel and P-channel devices that are isolated from each other. The N- and P-channel device separation assists in preventing device latch-up. N- and N-channel devices are isolated by controlling the process due to high field inversion thresholds and radiation hardened field oxide to eliminate any channel-to-channel leakage current after high dosage irradiation. A relatively thin gate oxide layer is formed over the islands, and the island edges are covered with phosphoroborosilicate glass deposited at a relatively low temperature (850.degree. C.) to eliminate sharp island edges and hence edge leakage. The use of SIMOX substrate materials, phosphoroborosilicate glass and thin oxide provides the benefits of improved speed and reduced leakage due to intrinsic oxide isolation, shallow wells and source and drain junctions. The use of a thin thermal oxide layer and phosphoroborosilicate glass eliminates the edge leakage and channel-to-channel leakage upon high dosage irradiation, thus providing improved radiation hardness. The method of the present invention provides for devices having stable field behavior after irradiation. The method produces radiation hardened devices that exhibit high speed and reliability and which are stable when irradiated with up to a 10 MRad dosage level.

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Abbas, S. A. et al., "Silicon-On-Sapphire . . . ", IBM Technical Disclosure Bulletin, vol. 16, No. 3, Aug. 1973, pp. 1027-1029.

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