Process protection for individual device gates on large area MIS

Details Process protection for individual device gates on large area MIS Process protection for individual device gates on large area MIS

1984-03-19

1986-07-08

James, Andrew J.

357 51, H01L 2978

Patent

active

045996393

ABSTRACT:
Gates of individual devices on a slice are connected through a resistance to the device substrate, and through the same resistance to other device gates. This interconnection and high-resistance drain gives the gate protection from static charge buildup and subsequent catastrophic discharge which would result in a faulty device. This method protects each gate from the time of deposition to final device packaging.

REFERENCES:
patent: 3676742 (1972-07-01), Russel et al.
patent: 4202001 (1980-05-01), Reichert et al.
patent: 4261004 (1981-04-01), Masuhara et al.
patent: 4426658 (1984-01-01), Gontowski
IBM Technical Disclosure Bulletin, vol. 19, #4, Sep. 1976 "Monolithic Integrated Circuit Fuse Link" by Deliduka et al.

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