Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1985-11-26

1987-11-17

Edlow, Martin H.

357 235, 357 45, 357 65, 357 68, 357 71, H01L 2978, H01L 2188, H01L 2944, H01L 2176

Patent

active

047077174

ABSTRACT:
A semiconductor integrated circuit memory device in which FET memory transistor cells are disposed in a matrix wherein the source diffusion channels form a data path for each column of cells while the drain diffusion channels and gate electrodes are used for row and column addressing, respecitvely, and has extremely reliable ohmic contacts by virtue of a different pattern of the field insulating film used in the manufacturing process, as a result of which the depth of a source contact hole and a drain contact hole are substantially equal.

REFERENCES:
patent: 4289834 (1981-09-01), Alcorn et al.
patent: 4471373 (1984-09-01), Shimizu et al.
"A High-Denisty, High-Performance EEPROM Cell, Schauer et al., IEEE Transactions on Electron Devices, vol. Ed-29, No. 8, Aug. 1982.

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