Data word normalization

Details Data word normalization Data word normalization

1982-12-13

1986-04-29

Thomas, James D.

Boots, shoes, and leggings

G06F 738

Patent

active

045861544

ABSTRACT:
A data word (bits ID.0.-ID15) is supplied to the address inputs of a memory arrangement U1, U2, U3 whose outputs S0-S3 supply to a parallel shifter SN a control word specifying the number of shifts required. As described, two read-only memories receive respective halves of the data word and feed a multiplexer U3 which selects the outputs of U1 unless the latter indicating that all its inputs are zero (or one, for negative numbers) in which case control is passed to U2. The sign bit (ID15) is supplied to both memories.

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patent: 4334284 (1982-06-01), Wong
Freiman et al., "Normalized Integer Operations for a Floating Point Arithmetic Unit", IBM Technical Disclosure Bulletin, vol. 9, No. 7, Dec. 1966, pp. 850-851.
Gooding et al., "Handling Leading Zeros in a Data Processing Unit", IBM Technical Disclosure Bulletin, vol. 17, No. 10, Mar. 1975, pp. 2844-2845.
"Am25S10 Four-Bit Shifter With Three-State Outputs" In: Advanced Micro Devices Bipolar Microprocessor Logic and Interface Data Book, Sunnyvale, Calif., Advanced Micro Devices, Inc., 1981, pp. 3-15 to 3-18.
Mick, J. R., "Am25S10 Four-Bit Shifter" In: Advanced Micro Devices Bipolar Microprocessor Logic and Interface Data Book, Sunnyvale, Calif., Advanced Micro Devices, Inc., 1981, pp. 3-19 to 3-28.

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