Methods of making semiconductor chip assemblies

Metal working – Method of mechanical manufacture – Electrical device making

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

29832, 29840, 29842, 438113, H05K 330, H01L 2160

Patent

active

058484671

ABSTRACT:
Semiconductor chip assemblies are fabricated by providing a wafer having a plurality of semiconductor chips and providing a sheet separate from the wafer having a plurality of dielectric elements. Each chip has a plurality of contacts and each dielectric element has a plurality of terminal formed thereon. The sheet and the wafer are then assembled so that the terminals on the dielectric elements face away from the wafer and so that each chip is associated with a dielectric element. The contacts on each chip are connected to the terminals on a dielectric element associated with the chip. The individual dialectic elements are then severed from the sheet and the individual chips are severed from the wafer after the assembling and connecting step to provide subassemblies, each subassembly including a chip and the dielectric element associated with the chip. In another embodiment, a plurality of individual dielectric elements separate from one another and separate from a wafer are provided.

REFERENCES:
patent: Re35119 (1995-12-01), Blonder et al.
patent: T955008 (1977-02-01), Gregor et al.
patent: 3753289 (1973-08-01), Berner
patent: 3823467 (1974-07-01), Shamash et al.
patent: 3825353 (1974-07-01), Loro
patent: 3952404 (1976-04-01), Matunami
patent: 4189825 (1980-02-01), Robillard et al.
patent: 4349862 (1982-09-01), Bajorek et al.
patent: 4536469 (1985-08-01), Alderstein
patent: 4648179 (1987-03-01), Bhattacharyya et al.
patent: 4655524 (1987-04-01), Etzel
patent: 4658332 (1987-04-01), Baker et al.
patent: 4681654 (1987-07-01), Clementi et al.
patent: 4695870 (1987-09-01), Patraw
patent: 4700473 (1987-10-01), Freyman et al.
patent: 4766670 (1988-08-01), Godzik et al.
patent: 4772936 (1988-09-01), Reding et al.
patent: 4783695 (1988-11-01), Eichelberger et al.
patent: 4847146 (1989-07-01), Yeh et al.
patent: 4855872 (1989-08-01), Wojner et al.
patent: 4860088 (1989-08-01), Smith et al.
patent: 4866841 (1989-09-01), Hubbard
patent: 4890157 (1989-12-01), Wilson
patent: 4890383 (1990-01-01), Lumbard et al.
patent: 4893172 (1990-01-01), Matsumoto et al.
patent: 4914815 (1990-04-01), Takada et al.
patent: 4930216 (1990-06-01), Nelson
patent: 4937653 (1990-06-01), Blonder et al.
patent: 4954878 (1990-09-01), Fox et al.
patent: 4975765 (1990-12-01), Ackermann et al.
patent: 4993954 (1991-02-01), Provost
patent: 5006673 (1991-04-01), Freyman et al.
patent: 5023205 (1991-06-01), Reche
patent: 5029325 (1991-07-01), Higgins, III et al.
patent: 5055907 (1991-10-01), Jacobs
patent: 5070297 (1991-12-01), Kwon et al.
patent: 5086337 (1992-02-01), Noro et al.
patent: 5117275 (1992-05-01), Bregman et al.
patent: 5139972 (1992-08-01), Neugebauer et al.
patent: 5192716 (1993-03-01), Jacobs
patent: 5210939 (1993-05-01), Mallik et al.
patent: 5217916 (1993-06-01), Anderson et al.
patent: 5346861 (1994-09-01), Khandros et al.
patent: 5455390 (1995-10-01), DiStefano et al.
patent: 5518964 (1996-05-01), DiStefano et al.
Research Disclosure No. 322 Feb. 1991 p. 130 "Method of Testing Chips and Joining Chips to Substrates".
IBM Technical Disclosure Bulletin entitled "Non-Permanent Mounting Technique for Test and Burn-In of C4 Devices", Nov. 1990, vol. 33, No. 7.
IBM Technical Disclosure Bulletin, entitled "Extended Pad For Testing Package Parts", Dec. 1984, vol. 27, No. 7B.
IBM Technical Disclosure Bulletin entitled Test and Repair of Direct Ship Attach Modules, Aug. 1988, vol. 31, No. 3.
IBM Technical Disclosure Bulletin entitled "Design For Minimum Chip Joint Street", Dec. 1989, vol. 32, No. 7.
IBM Technical Disclosure Bulletin entitled Improved C4 Reliability Using Law Modulus Dielectric Layer, Nov. 1989, vol. 32, No. 6A.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods of making semiconductor chip assemblies does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of making semiconductor chip assemblies, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of making semiconductor chip assemblies will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1449501

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.