Method for the manufacture of integrated MOS-field effect transi

Details Method for the manufacture of integrated MOS-field effect transi Method for the manufacture of integrated MOS-field effect transi

1983-01-17

1985-04-16

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

357 67, 357 71, 148174, H01L 21285

Patent

active

045106703

ABSTRACT:
A method for the manufacture of integrated MOS-field effect transistor circuits in silicon gate technology and wherein diffusion source and drain zones are coated with a high melting point silicide as low-impedance printed conductors. The diffusion zones and polysilicon gates are made low-impedance through selective deposition of the metal silicide onto surfaces thereof. The selective deposition, which proceeds by use of a reaction gas eliminating hydrogen halide, simplifies the process sequence and is fully compatible with conventional silicon gate processes. Because of the high temperature stability, preferably tantalum silicide is employed. The invention is useful in the manufacture of MOS-circuits in VLSI-technology.

REFERENCES:
patent: 4283439 (1981-08-01), Higashinakagawa et al.
patent: 4330931 (1982-05-01), Liu
patent: 4343081 (1982-08-01), Lepsetter et al.
patent: 4359490 (1982-11-01), Lehrer
patent: 4384301 (1983-05-01), Tasch, Jr. et al.
Muraka "Refractory Silicides for Integrated Circuits" J. Vac. Sci. Technol., 17(4), Jul./Aug. 1980.
T. Shibata et al., Proceedings of IEMD 81, Paper No. 28.2, pp. 647 to 650, Entitled "An Optimally Designed Process for Submicron MOSFETS".
P. A. Gargini et al., Proceedings of IEMD 81, Paper No. 3.2, p. 54, Entitled "Low Resistance Self-Sligned Source, Drain and Gate Transistors".

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