Digital signal processor having duplex working registers for swi

Details Digital signal processor having duplex working registers for swi Digital signal processor having duplex working registers for swi

1991-08-27

1993-06-22

Kriess, Kevin A.

Boots, shoes, and leggings

364DIG1, 3642632, 364268, 3642683, 3642685, 3642443, 364244, 3642624, 3642628, 364247, G06F 900, G06F 1116

Patent

active

052222411

ABSTRACT:
A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

REFERENCES:
patent: 3905025 (1975-09-01), Davis et al.
patent: 4338662 (1982-07-01), Yokoyama
patent: 4438492 (1984-03-01), Harmon, Jr. et al.
patent: 5021993 (1991-06-01), Matoba et al.
patent: 5050076 (1991-09-01), Misaka

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