Pipeline computer system having write order preservation

Details Pipeline computer system having write order preservation Pipeline computer system having write order preservation

1990-08-27

1993-06-22

Lee, Thomas C.

Boots, shoes, and leggings

3642409, 364271, 3649354, 3649402, 36494081, 395575, G06F 1300, G06F 1336, G06F 1342

Patent

active

052222195

ABSTRACT:
A method for preserving data transfer order in a pipeline computer system, wherein a first block of data is transferred from a first device to at least a second device during a first computer cycle. Simultaneously, the first block of data is stored within the first device. Druing a second computer cycle, a second block of data is transferred from the first device to the second device, and an acknowledge signal is issued, indicating the success or failure of the transfer of the first block of data. If the acknowledge signal indicates a failed data transfer, a reject signal is issued and data transfer is restarted beginning with the previously failed data transaction which has been stored within the first device, and data transfer then continues with a preserved data transfer order.

REFERENCES:
patent: 4419724 (1983-12-01), Branigin et al.
patent: 4547849 (1985-10-01), Louie et al.
patent: 4587609 (1986-05-01), Boundreau et al.
patent: 4768145 (1988-08-01), Wheelwright

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