Partial product accumulation in high performance multipliers

Details Partial product accumulation in high performance multipliers Partial product accumulation in high performance multipliers

1982-10-13

1985-10-01

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

045450285

ABSTRACT:
A new technique for the accumulation of partial product terms in a monolithic VLSI multiplier is disclosed. The method requires fewer than a 5% increase in transistors over older techniques yet provides more than three times the performance of the prior art when used to implement a 64.times.64 multiplier. The accumulator is implemented with one-bit cells to facilitate the VLSI mask design and is expandable to any desired precision.

REFERENCES:
patent: 4153938 (1979-05-01), Chest et al.
Waser, "High-Speed Monolithic Multipliers for Real-Time Digital Signal Processing", Computer, Oct. 1978, pp. 19-29.
Goshing et al., "Uncommitted Logic Array which Provides Cost-Effective Multiplication Even for Long Words", Computers & Digital Techniques, Jun. 1979, vol. 2, No. 3, pp. 113-120.
Andrew D. Booth, "A Signed Binary Multiplication Technique", Quarterly Journ. Mech. and Applied Math., vol. IV, Pt. 2 (1951), pp. 236-240.
C. S. Wallace, "A Suggestion for a Fast Multiplier", IEEE Transactions on Electronic Computers, pp. 14-17 (Feb. 1964).

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