Self-testing dynamic RAM

Details Self-testing dynamic RAM Self-testing dynamic RAM

1990-07-12

1993-11-16

Atkinson, Charles E.

Excavating

371 212, 371 681, G01R 3128

Patent

active

RE0344451

ABSTRACT:
Very large dynamic RAM integrated circuits are rendered self-testing by using on-chip generation of data test patterns with very high fault coverage, and concurrent testing of storage cell subarrays to reduce overall testing time. A test generator, which may operate in combination with the refresh control and timing system of the RAM integrated circuit, supplies the initial data test pattern which is loaded into the storage arrays. The conventional sense amplifier array is modified, and coupled with a gate control system for shifting data in each column of each storage subarray to an adjacent column. Alternatively, a two-terminal bilateral storage cell may be used to effect the shifting function, which effectively converts the memory into a shift register. The use of complementary data test patterns will permit detection of symmetrical faults within storage arrays.

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Konemann et al., Built-In Test for Complex Digital Integrated Circuits, Fifth European Solid State Circuits Conference, pp. 89-90, 18-21 Sep. 1979.
LeBlanc, LOCST: A Built-In Self-Test Technique, IEEE Design and Test, Nov. 1984, pp. 45-52.

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