Programmable clock having programmable delay and duty cycle base

Details Programmable clock having programmable delay and duty cycle base Programmable clock having programmable delay and duty cycle base

1994-07-18

1996-04-09

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Comparing counts

377 55, 377 56, 327151, H03K 2108

Patent

active

055068782

ABSTRACT:
An input clock delay circuit includes an up counter for estimating the approximate number of internal clock cycles that occur during one cycle of the input clock signal and another up counter for determining the portion of each cycle of the input clock signal that is high. A clock manipulation circuit receives each counter's value, and may be set to perform a fixed transform on the input clock signal, such as clock delay/advance, duty cycle shifting, and frequency multiplication/division. The clock manipulation circuit output values are loaded into two down counters that are also clocked by the internal clock. On the rising edge of the input clock signal, the first down counter starts decrementing until the counter reaches zero, indicating that the desired delay interval has passed, at which point the delayed output clock signal is taken high. The second down counter then starts decrementing for an interval that is equal to the desired duty cycle of the output clock signal. When the second down counter reaches zero, the output clock signal is taken low, and the process repeats.

REFERENCES:
patent: 4322643 (1982-03-01), Preslar
patent: 4754163 (1988-06-01), Aue et al.
patent: 4809221 (1989-02-01), Magliocco et al.
patent: 5109394 (1992-04-01), Hjerpe et al.
patent: 5173617 (1992-12-01), Alsup et al.
patent: 5345489 (1994-09-01), Saitoh
Alex Waizman, "A Delay Line Loop for Frequency Synthesis of De-Skewed Clock", pp. 298-299, ISSCC94/Session 18/High-Performance Logic and Circuit Techniques/Paper FA 18.5, IEEE International Solid-State Circuits Conference, 1994.
Thomas H. Lee, Kevin Donnelly, John Ho, Jared Zerbe, Mark Johnson, and Toru Ishikawa, "A 2.5V Delay-Locked Loop for an 18Mb 500MB/s DRAM", pp. 300-301, ISSCC94/Session 18/High Performance Logic & Circuit Techniques/Paper FA 18.6, IEEE International Solid-State Circuits Conference, 1994.
Avner Efendovich, Yachin Afek, Coby Sella, and Zeev Bikowsky, "Multi-Frequency Zero-Jitter Delay-Locked Loop", pp. 27.1.1-27.1.4, IEEE 1993 Custom Integrated Circuits Conference.

Affiliated with

Also associated with

Rating

Programmable clock having programmable delay and duty cycle base does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable clock having programmable delay and duty cycle base, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable clock having programmable delay and duty cycle base will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-144470