Semiconductor memory device capable of performing an overall tes

Details Semiconductor memory device capable of performing an overall tes Semiconductor memory device capable of performing an overall tes

1994-03-17

1996-04-09

Nguyen, Hoa T.

Excavating

G06F 1116

Patent

active

055068499

ABSTRACT:
Disclosed is a semiconductor memory device. A read control signal is externally input in read mode, and a test mode signal is externally input in a mode for testing memory cells. Based on the input read control signal, plural pieces of read data read out from a plurality of memory cells are latched by a plurality of latch circuits. Output signals of the latch circuits are input to a data compressor, which checks if the output signals of the latch circuits are the same and outputs a resultant signal in a form of compressed data of one bit. The output signal of the data compressor is input to an output circuit, which outputs the output signal of the data compressor based on the input test mode signal. A preset circuit allows the latch circuits to latch different pieces of data based on the test mode signal and the read control signal.

REFERENCES:
patent: 4464750 (1984-08-01), Tatematse
patent: 4899313 (1990-02-01), Kumanoya et al.
patent: 4916700 (1990-04-01), Ito et al.
patent: 5148398 (1992-09-01), Kohno
patent: 5361230 (1994-11-01), Ikeda et al.

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