Logical circuit array

Details Logical circuit array Logical circuit array

1983-10-20

1986-04-15

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307469, 307481, 364716, H03K 19177, H03K 19096, H03K 1920, G06F 748

Patent

active

045830126

ABSTRACT:
A logical circuit array is provided in which the AND and OR planes are folded together and all of the logic cell transistor gates are oriented in the same direction. The array comprises a plurality of AND rows R.sub.0 through R.sub.n, and means for precharging the AND rows to one logic level, e.g. V.sub.DD. An additional row R.sub.a is provided along with means for precharging the additional row to another logic level, e.g., ground. The array includes a plurality of data columns and an output column coupled to AND row R.sub.0. A plurality of logic cells is divided among AND rows R.sub.0 through R.sub.n-1. Each of the logic cells has an input terminal coupled to a data column, a first output terminal connected to the AND row with which the logic cell is associated, and a second output terminal connected to the next successive AND row in the array. A plurality of logic cells is associated with AND row R.sub.n, with each such cell having an input terminal coupled to a data column, a first output terminal connected to AND row R.sub. n, and a second output terminal connected to additional row R.sub.a. In the array, the AND conditions of signals on the data columns are formed on the AND rows by the logic cells associated therewith, and the OR condition of the AND rows is formed on the output column.

REFERENCES:
patent: 4207616 (1980-06-01), Heeren
patent: 4208728 (1980-06-01), Blahut et al.
patent: 4409499 (1983-10-01), Zapisek et al.
patent: 4501977 (1985-02-01), Koike
patent: 4506341 (1985-03-01), Kalter

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