Semiconductor device with self-aligned gate structure and manufa

Details Semiconductor device with self-aligned gate structure and manufa Semiconductor device with self-aligned gate structure and manufa

1986-09-11

1988-04-12

Carroll, J.

357 234, 357 2311, 357 49, 357 55, 357 41, 357 65, 357 68, H01L 2978, H01L 2702, H01L 2906, H01L 2348

Patent

active

047378310

ABSTRACT:
A semiconductor device having a new structure of source and drain regions. A semiconductor device of the present invention includes a semiconductor substrate of a first conductivity type, an impurity region of a second conductivity type formed on the semiconductor substrate, and a metal pattern formed on the impurity region and isolated by a plurality of grooves. A gate insulation film is formed on the bottom and the inner wall of at least one of the grooves, and a conductor to be a gate electrode is formed on the gate insulation film to be buried in this groove.

REFERENCES:
patent: 3648125 (1972-03-01), Peltzer
patent: 4108686 (1978-05-01), Jacobas, Jr.
patent: 4206005 (1980-06-01), Yeh et al.
patent: 4324038 (1982-04-01), Chang et al.
patent: 4462040 (1984-07-01), Ho et al.
patent: 4513303 (1985-04-01), Abbas et al.
C. G. Jambotkas, "High-Performance FET Technology", IBM Technical Disclosure Bulletin, vol. 23 (1981), pp. 4950-4953.

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