Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Identifying or correcting improper counter operation
Patent
1989-04-26
1990-12-18
Heyman, John S.
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Identifying or correcting improper counter operation
377 55, H03K 2140
Patent
active
049791931
ABSTRACT:
A multi-stage M-bit binary counter is disclosed including S counter stages in which each counter stage includes an N-bit counter (M=S.times.N). During a test operation, the stages are decoupled for individual operation, a count value is loaded into the N-bit counter provided in each of the stages, and the N-bit counters of each stage are clocked 2.sup.N times to check independently the function of the N-bit counters. The stages are then coupled together to function as a multi-stage M-bit counter and a single clock pulse is supplied to the M-bit counter to check the carry propagation between stages. If the N-bit counters are of a type which only generate an output when fully incremented or decremented and the actually count value cannot be read from the M-bit counter, then the stages are decoupled together for a second time and the N-bit counters are clocked an additional 2.sup.N times.
REFERENCES:
patent: 4611337 (1986-09-01), Evans
patent: 4661930 (1987-04-01), Tran
patent: 4736395 (1988-04-01), Sugihara
patent: 4745630 (1988-05-01), Underwood
patent: 4759043 (1988-07-01), Lewis
patent: 4852130 (1989-07-01), Draxelmayr
Advanced Micro Devices , Inc.
Heyman John S.
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