High voltage depletion mode transistor with serpentine current p

Details High voltage depletion mode transistor with serpentine current p High voltage depletion mode transistor with serpentine current p

1986-01-13

1987-07-14

Carroll, J.

357 20, 357 41, 357 52, H01L 2906, H01L 2978, H01L 2702, H01L 2934

Patent

active

046806059

ABSTRACT:
A depletion mode MOS transistor which can function like a constant current source, when its gate is connected to the source and its drain is held at a fixed voltage even above 40 volts. In addition to heavily doped source and drain regions and a lightly doped, gated channel region, all of one conductivity type, formed in a lightly doped substrate or region of the other conductivity type, the transistor includes thin, heavily doped fingers of the other polarity that extend outwardly from beneath the gate to the grounded barrier ring isolating the transistor from other devices in the substrate. The fingers eliminate the flow of parasitic source to drain currents normally existing between the sides of the gate electrode and the barrier, thus providing a depletion mode MOS transistor having an I.sub.SD vs. V.sub.S characteristic more like that of a constant current source when the gate is connected to the source.

REFERENCES:
patent: 3440502 (1969-04-01), Lin et al.
patent: 3602782 (1971-08-01), Klein
patent: 3643139 (1972-02-01), Nienhuis
patent: 3896483 (1975-07-01), Whelan
patent: 4247860 (1981-01-01), Tihanyi
patent: 4282539 (1981-08-01), Schrader
patent: 4350991 (1982-09-01), Johnson et al.
W. S. Johnson, "Multiple Masking Technique in Ion Implantation", IBM Technical Disclosure Bulletin, vol. 15 (1972), pp. 660-661.

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