Input/output port including auxiliary low-power transistors

Details Input/output port including auxiliary low-power transistors Input/output port including auxiliary low-power transistors

1986-08-19

1987-07-14

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307469, 307200B, 365227, H03K 17687

Patent

active

046804870

ABSTRACT:
A input/output port for use in a device such as a central processing unit includes a common input/output terminal which serves as an input terminal when the port is set in a data input mode and as an output terminal when the port is set in a data output mode. The common terminal is connected to the junction between a pair of transistors connected in series between a high voltage source and ground. Also provided is a third transistor having a lower capability or power than the pair of first and second transistors and connected between the high voltage source and the common terminal. During data output mode, the pair of first and second transistors is turned on and off in a complementary fashion in accordance with data to be output. During data input mode, the pair of first and second transistors is maintained turned off and the third transistor is set either turned off or turned on.

REFERENCES:
patent: 4301383 (1981-11-01), Taylor
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patent: 4465945 (1984-08-01), Yin
patent: 4479067 (1984-10-01), Fujita
patent: 4523106 (1985-06-01), Tanizawa et al.
patent: 4581551 (1986-04-01), Campbell, Jr.
patent: 4591742 (1986-05-01), Morito
patent: 4621208 (1986-11-01), van Tran
Harrod et al, "Ungated Common I/O Buffer for Card Testing", IBM T.D.B., vol. 21, No. 6, Nov. 1978, pp. 2476-2477 (307/475).

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