Protective arrangement for MOS circuits

Details Protective arrangement for MOS circuits Protective arrangement for MOS circuits

1988-10-06

1989-11-21

James, Andrew J.

357 51, H01L 2978

Patent

active

048826103

ABSTRACT:
In this protective arrangement, a resistor between a pad (p) and a transistor to be protected is implemented with an expansion region (e) which lies completely below the pad (p) and extends beyond the latter along the entire circumference of the pad. An elongate region (z) extends along the circumference of the expansion region (e) and is connected to circuit ground via an interconnection track (b). The connection between the elongate region (z) and the interconnection track (b) has a low resistance.

REFERENCES:
patent: 4509067 (1985-04-01), Minami et al.
patent: 4757363 (1988-07-01), Bohm et al.
Proceedings of the 1980 Electrical Overstress/Electrostatic Discharge Symposium, 1980, pp. 73-80, J. K. Keller: "Protection of MOS Integrated Circuits from Destruction by Electrostatic Discharge".

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