Complementary power saving comparator/inverter circuits

Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock

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Details

307251, 307358, 330253, 330264, H03K 1730, H03K 1760, H03F 345, H03K 1704

Patent

active

041031903

ABSTRACT:
A CMOS power saving comparator/inverter circuit includes a complementary differential amplifier, one input of which is coupled to a voltage input. Another input of the complementary differential amplifier is coupled to a voltage reference circuit which includes two relatively high value resistors coupled in series between a P-channel MOSFET coupled to the positive voltage conductor and N-channel MOSFET coupled to the ground voltage conductor. An output of the differential amplifier is connected to an input of a CMOS inverter having its output connected to an output of the comparator/inverter circuit. The transition point, defined as the value of input voltage at which the output voltage is equal to one-half of the supply voltage, is virtually independent of the P-channel and N-channel threshold voltages. The transition point is much sharper than the transition point for a conventional CMOS inverter, and much less dependent upon various manufacturing parameter variations. The DC current of the circuit drops to zero when the input is at V.sub.DD or at ground.

REFERENCES:
patent: 3943380 (1976-03-01), Morgan et al.
patent: 3947778 (1976-03-01), Hsiao et al.
patent: 3956708 (1976-05-01), Musa
patent: 3961279 (1976-06-01), Davis
patent: 3984780 (1976-10-01), Hsiao et al.
patent: 4004158 (1977-01-01), Morgan

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