Method of jointly forming stacked capacitors and antifuses, meth

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

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257532, 438467, 438600, 438622, H01L 2900

Patent

active

057264830

ABSTRACT:
A method of jointly forming stacked capacitors and antifuses includes, a) providing a common layer of electrically conductive material to form both a capacitor storage node and an inner antifuse plate; b) providing a common layer of dielectric material over the capacitor storage node and the inner antifuse plate, the common layer of dielectric material comprising both an intervening capacitor dielectric element and an intervening antifuse dielectric element, the common layer of dielectric material having a first breakdown voltage per unit length value for a given current per unit area; c) providing a common layer of electrically conductive material over the common layer of dielectric material to form both a capacitor cell layer and an outer antifuse plate; d) providing a lateral edge of the outer antifuse plate and a lateral edge of the intervening antifuse dielectric element; and e) depositing an antifuse breakdown layer of dielectric material over the lateral edges of the outer antifuse plate and the intervening antifuse dielectric element, the antifuse breakdown layer having a second breakdown voltage per unit length value for the same given current per same unit area which is lower than said first breakdown voltage per unit length value. Novel antifuse constructions, integrated circuitry and method of blowing antifuses are also disclosed.

REFERENCES:
patent: 5196724 (1993-03-01), Gordon et al.
patent: 5208177 (1993-05-01), Lee
patent: 5219782 (1993-06-01), Liu et al.
patent: 5557136 (1996-09-01), Gordon et al.
patent: 5592016 (1997-01-01), Go et al.

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