Method of manufacturing a heterojunction bipolar transistor havi

Metal working – Method of mechanical manufacture – Assembling or joining

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29571, 148 15, 148175, 148187, 148DIG10, 148DIG84, 357 16, 357 34, H01L 21265

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046793054

ABSTRACT:
A method of manufacturing a heterojunction bipolar transistor comprising the steps of forming a first semiconductor layer of a first conductivity type as a collector on a semiconductor substrate, forming a second semiconductor layer of a second conductivity type as a base on the first semiconductor layer, forming a third semiconductor layer of the first conductivity type as an emitter on the second semiconductor layer, the third and second semiconductor layers constituting a heterojunction, selectively forming a first mask on the third semiconductor layer, ion-implanting ions of an impurity of the second conductivity type into the resultant structure using a first mask, thereby forming an external base region of the second conductivity type extending to the second semiconductor layer, forming a second mask on a side wall of the first mask, and ion-implanting a predetermined material into the resultant structure using the first and second masks, thereby forming a high-resistance layer for isolating the external base region in self-alignment with the emitter.

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patent: 4617724 (1986-10-01), Yokoyama et al.
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IEEE Electron Device Letters, vol. EDL-4, No. 4, Apr. 1983, pp. 81-84, IEEE, New York, US; P. M. Asbeck, et al.: "Application of thermal pulse annealing to ion-implanted GaAlAs/GaAs Heterojunction bipolar transistors".
W. P. Dumke, et al; "GaAs-GaAlAs Heterojunction Transistor for High Frequency Operation", Solid-State Electronics, 1972, vol. 15, pp. 1139-1343.
T. Furutuka, et al; "Performance of Sidewall-Assisted Closley-Spaced Electrode GaAs MESFETs", National Converntion Record; 1984, IECE of Japan, Part 2, p. 24.
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