Method and apparatus for selectable parallel execution of test o

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3241581, 371 221, G01R 3128

Patent

active

054973791

ABSTRACT:
The invention permits selectively enabling a plurality of circuits to synchronously enter and execute test operations based on a given test bus. A test bus controller (15) is enabled to simultaneously initiate test operations on two or more selected circuits (17) coupled to the test bus (11) via a connection device (19) and a connection protocol.

REFERENCES:
patent: 5388104 (1995-02-01), Shirotori et al.
patent: 5396170 (1995-03-01), D'Souza et al.

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