Reducing the number of carry-look-ahead adder stages in high-spe

Details Reducing the number of carry-look-ahead adder stages in high-spe Reducing the number of carry-look-ahead adder stages in high-spe

1993-08-05

1996-03-05

Malzahn, David H.

Boots, shoes, and leggings

364745, G06F 750

Patent

active

054973430

ABSTRACT:
A carry-look-ahead adder for adding an addend and an augend and generating a final sum. The addend, augend, and final sum are binary numbers, each having a plurality of bits. Bits of the same order in the addend and the augend are organized into columns. The adder has at least one data reduction stage, each data reduction stage having at least one multi-column full adder. The data reduction stages use the columns of addend and augend bits to generate a reduced addend and a reduced augend, with the reduced augend having fewer bits than the augend. A generate/propagate calculation stage then uses the reduced addend and the reduced augend for calculating generate and propagate data, the generate/propagate calculation stage having been modified to account for the reduction of the addend and augend. A carry-generate stage then uses the generate and propagate data to generate at least one final carry. Finally, a final sum calculation stage uses the reduced addend, the reduced augend, and the final carries for calculating the final sum. The data reduction stages reduce the inputs to the generate/propagate calculation stage thereby reducing the number of inputs to the carry-generate circuit. With fewer inputs, the number of stages in the carry-generate circuit can be reduced, thus resulting in a faster implementation of the carry-look-ahead adder.

REFERENCES:
patent: 4623981 (1986-11-01), Wolrich et al.
patent: 4660165 (1987-04-01), Masumoto
patent: 4764886 (1988-08-01), Yano
patent: 4949297 (1990-08-01), Matsuoka
patent: 5278783 (1994-01-01), Edmondson

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